The parallel resistance of R2 and the reflection of R3 at the base of the PNP transistor (let's call this R_parallel) forms a voltage divider with R1 to provide a control voltage at the base of the transistor.
The voltage drop at the emitter resistor of the PNP transistor is the supply voltage Vcc (minus) the base voltage (minus) base-emitter junction voltage of 0.6. The charging current supplied to the capacitor will be this voltage drop (divided by) R3 (minus) the base-emitter bias current.
The current source becomes a "constant-current" source if the control voltage is maintained at a constant level. The terminal voltage of a capacitor that is charged from a "constant-current" source will be a linear ramp, when plotted with respect to time.
The sawtooth generated by this circuit will go from 1/3rd of 5V to 2/3rd of 5V. In the actual circuit for the thyristor, provisions must be made to prevent the capacitor voltage from rising before the arrival of the next "zero-crossing".
In this example, care must be made to prevent the voltage applied to pin nos. 2 and 6 from going beyond 5 volts.
The output of this circuit (pin no. 3) is TTL-compatible.
