Data Transmission Implementation
Paul Lou C. Canlas
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Data transmission is implemented using shift registers and multiplexers. In the Diagram, eight 74LS194 (4-bit bidirectional shift registers) are used. The four inputs in each register are the data coming from the presence detection circuit. All registers are commonly cleared and S1'd (engaged in the S1 mode). This means that they load simultaneously, as well as engage in the shift right mode. They are also commonly clocked so that they're shifting may proceed simultaneously and synchronously. The least significant bit of each of their output is connected to an input bit of the 74LS153. The least significant bits of the first four register comprise the first four input of the multiplexer while the least significant bits of the last four register serve as the second four input of the multiplexer. The selector of multiplexer then determines which of these input is to be read or in what order are they to be read.
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